Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method

ABSTRACT

A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-186311, filed Jun. 27, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to design and manufacturing method of asemiconductor device (a semiconductor integrated circuit) and, moreparticularly, to a semiconductor device pattern creation method, patterndata processing method, pattern data processing program, andsemiconductor device manufacturing method.

2. Description of the Related Art

Along with the recent increase in the degree of integration and theoperation speed of semiconductor integrated circuits, requirements ofmicrofabrication in device pattern formation are becoming very rigorous.However, shortening the irradiation light wavelength in exposureapparatuses or the increase in numerical aperture (NA) of opticalsystems cannot sufficiently meet the requirements of microfabrication,and the margin necessary in the lithography process is hard to ensure.For this reason, it is important to increase the accuracy of aresolution enhancement technique (RET) and optical proximity correction(OPC). However, the margin can hardly be ensured even using RET and OPC.The difficulty of the lithography process to achieve microfabricationincreases, posing a serious problem of increase in lithography cost.

The requirements of microfabrication are especially conspicuous in adevice calls a system LSI. In designing a system LSI, a cell library isoften used in which a plurality of modules called cells with individualfunctions are gathered. In chip design, cell patterns included in thecell library are placed on the basis of circuit information determinedby circuit design, and a predetermined function is implemented byrouting between or in the placed cells (e.g., Jpn. Pat. Appln. KOKAIPublication No. 6-291186). To shrink the chip area, individual cellpatterns must be shrunk. To shrink the cell patterns, the device patternmust be microfabricated. Hence, the difficulty of the lithographyprocess inevitably increases.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda semiconductor device pattern creation method comprising: extracting acorrection target pattern having a size not more than a threshold valuefrom first design data containing a pattern of a semiconductor device;calculating a first characteristic of the semiconductor device on thebasis of the first design data; generating second design data bycorrecting the correction target pattern contained in the first designdata; calculating a second characteristic of the semiconductor device onthe basis of the second design data; checking whether a characteristicdifference between the first characteristic and the secondcharacteristic falls within a tolerance; and deciding to use the seconddesign data to manufacture the semiconductor device when thecharacteristic difference falls within the tolerance.

According to a second aspect of the present invention, there is provideda semiconductor device pattern data processing method comprising:acquiring a size of an overlapping area of each of a plurality of cellsincluded in a cell library to be used to design a semiconductor device,the overlapping area being a region which is arranged inside the celland in which placement of a functional pattern to impart a function tothe cell is inhibited; creating first design data by placing theplurality of cells; calculating a first characteristic of thesemiconductor device on the basis of the first design data; extracting acorrection target region in which, of patterns formed by combining theoverlapping areas upon placing the plurality of cells, a pattern has asize not more than a threshold value; generating second design data bycorrecting the correction target region contained in the first designdata; calculating a second characteristic of the semiconductor device onthe basis of the second design data; checking whether a characteristicdifference between the first characteristic and the secondcharacteristic falls within a tolerance; and deciding to use the seconddesign data to manufacture the semiconductor device when thecharacteristic difference falls within the tolerance.

According to a third aspect of the present invention, there is provideda semiconductor device manufacturing method of forming a pattern of asemiconductor device by using a photomask, comprising: formation of thephotomask including extracting a correction target pattern having a sizenot more than a threshold value from first design data containing apattern of a semiconductor device, calculating a first characteristic ofthe semiconductor device on the basis of the first design data,generating second design data by correcting the correction targetpattern contained in the first design data, calculating a secondcharacteristic of the semiconductor device on the basis of the seconddesign data, checking whether a characteristic difference between thefirst characteristic and the second characteristic falls within atolerance, and deciding to use the second design data to manufacture thesemiconductor device when the characteristic difference falls within thetolerance.

According to a fourth aspect of the present invention, there is provideda pattern data processing program for designing a pattern of asemiconductor device, comprising: extracting a correction target patternhaving a size not more than a threshold value from first design datacontaining a pattern of a semiconductor device; calculating a firstcharacteristic of the semiconductor device on the basis of the firstdesign data; generating second design data by correcting the correctiontarget pattern contained in the first design data; calculating a secondcharacteristic of the semiconductor device on the basis of the seconddesign data; checking whether a characteristic difference between thefirst characteristic and the second characteristic falls within atolerance; and deciding to use the second design data to manufacture thesemiconductor device when the characteristic difference falls within thetolerance.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a schematic view showing a pattern creation system accordingto a first embodiment of the present invention;

FIG. 2 is a flowchart showing a pattern creation method according to thefirst embodiment of the present invention;

FIG. 3 is a first schematic view showing cells so as to explain thepattern creation method according to the first embodiment of the presentinvention;

FIG. 4 is a sectional view taken along a line IV-IV in FIG. 3 so as toexplain the pattern creation method according to the first embodiment ofthe present invention;

FIG. 5 is a second schematic view showing cells so as to explain thepattern creation method according to the first embodiment of the presentinvention;

FIG. 6 is a third schematic view showing cells so as to explain thepattern creation method according to the first embodiment of the presentinvention;

FIG. 7 is a fourth schematic view showing cells so as to explain thepattern creation method according to the first embodiment of the presentinvention;

FIG. 8 is a schematic view showing a pattern creation system accordingto a second embodiment of the present invention;

FIG. 9 is a flowchart showing a pattern creation method according to thesecond embodiment of the present invention;

FIG. 10 is a first schematic view showing cells so as to explain apattern data processing method according to a third embodiment of thepresent invention;

FIG. 11 is a second schematic view showing cells so as to explain thepattern data processing method according to the third embodiment of thepresent invention;

FIG. 12 is a flowchart showing the pattern data processing methodaccording to the third embodiment of the present invention;

FIGS. 13A to 13D are schematic views showing patterns included in cellsso as to explain a pattern data processing method according to a fourthembodiment of the present invention;

FIG. 14 is a schematic view showing cells so as to explain the patterndata processing method according to the fourth embodiment of the presentinvention;

FIG. 15 is a schematic view showing a cell pattern so as to explain thepattern data processing method according to the fourth embodiment of thepresent invention; and

FIG. 16 is a schematic view showing a cell pattern so as to explain apattern data processing method according to a fifth embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention will be described below withreference to the accompanying drawing. The same or similar referencenumerals denote the same or similar parts throughout the drawing. Thedrawing shows only schematic views in which the relationship between thethickness and the planar sizes and the ratio of thicknesses of layersare different from the actuality. Detailed thicknesses and sizes shouldbe determined by checking the following explanation. The views of thedrawing also include parts with different size relationships and ratios.

First Embodiment

A pattern creation system according to the first embodiment has acentral processing unit (CPU) 300, as shown in FIG. 1. The CPU 300comprises an extraction unit 341, first characteristic calculation unit342, correction data generation unit 343, second characteristiccalculation unit 344, check unit 345, and decision unit 346. Theextraction unit 341 extracts a correction target pattern having a sizeequal to or smaller than a threshold value from the first design data ofa semiconductor integrated circuit. The first characteristic calculationunit 342 calculates the first characteristic of the semiconductorintegrated circuit to be manufactured on the basis of the first designdata. The correction data generation unit 343 generates second designdata by correcting the correction target pattern contained in the firstdesign data. The second characteristic calculation unit 344 calculatesthe second characteristic of the semiconductor integrated circuit to bemanufactured on the basis of the second design data. The check unit 345checks whether the characteristic difference between the firstcharacteristic and the second characteristic falls within the tolerance.The decision unit 346 decides to use the second design data tomanufacture the semiconductor integrated circuit if the characteristicdifference (difference) falls within the tolerance.

A data storage device 200 is connected to the CPU 300. The data storagedevice 200 comprises a first design data storage unit 201, thresholdvalue storage unit 202, correction target pattern storage unit 203,first characteristic storage unit 204, second characteristic storageunit 205, second design data storage unit 206, and tolerance storageunit 207. The first design data storage unit 201 stores the first designdata. The threshold value storage unit 202 stores the threshold valuereferred to by the extraction unit 341. The correction target patternstorage unit 203 stores the correction target pattern extracted by theextraction unit 341. The first characteristic storage unit 204 storesthe first characteristic calculated by the first characteristiccalculation unit 342. The second characteristic storage unit 205 storesthe second characteristic calculated by the second characteristiccalculation unit 344. The second design data storage unit 206 stores thesecond design data generated by the correction data generation unit 343.The tolerance storage unit 207 stores the tolerance referred to by thecheck unit 345.

An input device 312, output device 313, program storage device 330, andtemporary storage device 331 are also connected to the CPU 300. As theinput device 312, for example, a keyboard and a pointing device such asa mouse can be used. As the output device 313, an image display devicesuch as a liquid crystal display or monitor and a printer can be used.The program storage device 330 stores, e.g., an operating system tocontrol the CPU 300. The temporary storage. device 331 successivelystores calculation results by the CPU 300.

As the program storage device 330 and temporary storage device 331, arecording medium such as a semiconductor memory, magnetic disk, opticaldisk, magnetooptical disk, or magnetic tape to record a program can beused.

A semiconductor integrated circuit manufacturing method using thepattern creation method according to the first embodiment will bedescribed next with reference to the flowchart shown in FIG. 2.

(a) In step S101, the extraction unit 341 shown in FIG. 1 reads out thefirst design data of the semiconductor integrated circuit from the firstdesign data storage unit 201. Next, the extraction unit 341 reads out athreshold value T from the threshold value storage unit 202. Thethreshold value T is, e.g., the minimum size of an implantation targetregion in the ion implantation process. However, the threshold value Tis not limited to this and may be a value obtained. by adding a marginto the minimum size. Alternatively, the threshold value T may be a valuethat satisfies 0.5≧T/(λ/NA) where λ is the wavelength of light inexposure, and NA is the numerical aperture of the projecting opticalsystem of an exposure apparatus used in exposure.

(b) In step S102, the extraction unit 341 extracts a correction targetpattern having a size W_(T) equal to or smaller than the threshold valueT from a plurality of patterns contained in the first design data. Theextracted correction target pattern is stored in the correction targetpattern storage unit 203. In step S103, the first characteristiccalculation unit 342 calculates the first characteristic of thesemiconductor integrated circuit to be manufactured on the basis of thefirst design data. The “first characteristic” includes at least one ofthe transistor characteristic, circuit characteristic, electricalcharacteristic, timing characteristic, wiring capacitancecharacteristic, and wiring resistance characteristic. For example, tocalculate the transistor characteristic, the first characteristiccalculation unit 342 predicts the structure of a transistor to bemanufactured on the basis of the first design data by process analysisusing an implantation model of a Monte Carlo method or a diffusion modelof a kinetic Monte Carlo method. The first characteristic calculationunit 342 also obtains the channel length of the transistor from thepredicted structure and calculates a threshold voltage and the like onthe basis of the channel length. The first characteristic calculationunit 342 stores the calculated first characteristic in the firstcharacteristic storage unit 204.

(c) In step S104, the correction data generation unit 343 reads out thefirst design data of the semiconductor integrated circuit from the firstdesign data storage unit 201. Next, the correction data generation unit343 corrects the correction target pattern extracted by the extractionunit 341. “Correction” indicates erasing the correction target patternitself. After erasing the correction target pattern, the correction datageneration unit 343 generates second design data by removing thecorrection target pattern from the first design data. The correctiondata generation unit 343 stores the generated second design data in thesecond design data storage unit 206.

(d) In step S105, the second characteristic calculation unit 344 readsout the second design data from the second design data storage unit 206.The second characteristic calculation unit 344 calculates the secondcharacteristic of the semiconductor integrated circuit to bemanufactured on the basis of the second design data. Like the firstcharacteristic, the “second characteristic” includes at least one of thetransistor characteristic, circuit characteristic, electricalcharacteristic, timing characteristic, wiring capacitancecharacteristic, and wiring resistance characteristic. The secondcharacteristic calculation unit 344 stores the calculated secondcharacteristic in the second characteristic storage unit 205.

(e) In step S106, the check unit 345 reads out the first characteristicfrom the first characteristic storage unit 204 and the secondcharacteristic from the second characteristic storage unit 205. Thecheck unit 345 also reads out a tolerance R from the tolerance storageunit 207. Next, the check unit 345 calculates the characteristicdifference between the first characteristic and the secondcharacteristic and checks whether the calculated characteristicdifference falls within the tolerance R. For example, assume that eachof the first characteristic and second characteristic is a timingcharacteristic. In this case, the check unit 345 checks, by comparingthe characteristic difference with the tolerance R, whether a delayfailure occurs in the manufactured semiconductor integrated circuit dueto the characteristic difference between the first characteristic andthe second characteristic. If the calculated characteristic differencefalls within the tolerance R, the flow advances to step S107. If thecalculated characteristic difference falls outside the tolerance R, theflow advances to step S108.

(f) If the calculated characteristic difference falls within thetolerance R, it means that the removed correction target pattern is apattern with a low significance and has no influence on thecharacteristic of the semiconductor integrated circuit. It also meansthat the semiconductor integrated circuit manufactured on the basis ofthe second design data is equivalent to the semiconductor integratedcircuit manufactured on the basis of the first design data. In thiscase, in step S107, the decision unit 346 decides to use the seconddesign data to manufacture the semiconductor integrated circuit.

(g) If the calculated characteristic difference falls outside thetolerance R in step S106, it means that the removed correction targetpattern is a significant pattern having influence on the characteristicof the semiconductor integrated circuit. It also means that thesemiconductor integrated circuit manufactured on the basis of the seconddesign data is not equivalent to the semiconductor integrated circuitmanufactured on the basis of the first design data. In this case, instep S108, the decision unit 346 decides to use the first design data tomanufacture the semiconductor integrated circuit.

(h) In step S111, the first design data or second design data decided touse is subjected to graphic data processing such as interlayer logicoperation, black/white inversion, overlap removal, narrowing/widening,and enlargement/reduction to create a mask pattern. In step S112, aphotomask having the mask pattern is manufactured by using, e.g., an EBlithography apparatus. Finally in step S113, a semiconductor integratedcircuit is manufactured by using the photomask, thus ending thesemiconductor integrated circuit manufacturing method according to thisembodiment.

According to the semiconductor integrated circuit manufacturing methodusing the pattern creation method according to the first embodimentshown in FIG. 2, when the characteristic difference between the firstcharacteristic and the second characteristic falls within the toleranceR, the second design data obtained by deleting the correction targetpattern having a size D_(T) equal to or smaller than the threshold valueT is used to manufacture the semiconductor integrated circuit. When thecorrection target pattern having the size D_(T) equal to or smaller thanthe threshold value T is contained in the design data, the difficulty ofthe lithography process increases, and the semiconductor integratedcircuit manufacturing cost increases. However, when the semiconductorintegrated circuit is manufactured on the basis of the second designdata, condition setting, maintenance, and the like in the lithographyprocess included in step S113 can be simplified because the correctiontarget pattern having the size D_(T) equal to or smaller than thethreshold value T is deleted. In pattern creation method according tothe first embodiment, it is verified in step S106 that even thesemiconductor integrated circuit manufactured on the basis of the seconddesign data is equivalent to the semiconductor integrated circuitmanufactured on the basis of the first design data. Hence, thesemiconductor integrated circuit manufacturing cost can be reducedwithout degrading the quality by using the second design data. Forexample, when the pattern creation method of the first embodiment isapplied to the development step of semiconductor integrated circuits of65-nm node generation, the lithography cost in the ion implantationprocess can be reduced to about ⅓ as compared to the prior-art method.

The semiconductor integrated circuit manufacturing method using thepattern creation method of the first embodiment is not limited to thesequence shown in FIG. 2. For example, step S102 may be executed afterstep S103. In the above description, “correction” in step S103 indicateserasing the correction target pattern itself. Instead, “correction” mayindicate correcting the size W_(T) equal to or smaller than thethreshold value T of the correction target pattern to a size W_(U)larger than the threshold value T. In this case, in step S104, thecorrection data generation unit 343 generates second design data bycorrecting the size W_(T) equal to or smaller than the threshold value Tof the correction target pattern in the first design data to the sizeW_(U) larger than the threshold value T. In addition, if thecharacteristic difference between the first characteristic and thesecond characteristic falls within the tolerance R in step S106, thedecision unit 346 decides to use the second design data containing thecorrected correction target pattern to manufacture the semiconductorintegrated circuit in step S107.

An application example of the pattern creation method of the firstembodiment will be described next with reference to FIGS. 3 to 7. FIG. 3and FIG. 4 showing a sectional view taken along a line IV-IV in FIG. 3show a first cell 21 and a second cell 22 which are contained in thefirst design data and are adjacent to each other. The first cell 21 hasan element region 41 surrounded by an element isolation region 31 andgates 51 a and 51 b arranged on the element region 41. The second cell22 has an element region 42 surrounded by an element isolation region 32and gates 52 a and 52 b arranged on the element region 42.

When an impurity such as phosphorus (p⁺) is to be implanted in part ofthe first cell 21 and second cell 22, a resist mask 25 having openingpatterns 26, 27, and 28 is placed on the first cell 21 and second cell22, as shown in FIG. 5. For this reason, as shown in FIG. 6, theimpurity is implanted in an implantation target region 126 correspondingto the opening pattern 26, an implantation target region 127corresponding to the opening pattern 27, and an implantation targetregion 128 corresponding to the opening pattern 28 on the basis of thedesign.

In the pattern creation method according to the first embodiment, when asize W of the opening pattern 28 and corresponding implantation targetregion 128 is the size W_(T) equal to or smaller than the minimum sizethreshold value T of the implantation target region in ion implantation,the second design data is generated by erasing the implantation targetregion 128 from the first design data, as shown in FIG. 7. However, ifthe characteristic does not change even when the semiconductorintegrated circuit is manufactured on the basis of the second designdata, providing the implantation target region 128 is of no significancein manufacturing the semiconductor integrated circuit. When thesemiconductor integrated circuit is manufactured on the basis of thesecond design data, the opening pattern 28 having the size W_(T) equalto or smaller than the minimum size threshold value T need not beprovided in the lithography process. For this reason, the difficulty ofthe lithography process can be decreased. As a result, the semiconductorintegrated circuit can be manufactured at a low cost.

Second Embodiment

A pattern creation system according to the second embodiment shown inFIG. 8 is different from FIG. 1 in that a CPU 300 further comprises amanufacturability verification unit 347, correction unit 348, opticalproximity correction unit 349, and correction verification unit 350, anda data storage device 200 further comprises a manufacturability storageunit 208, and third design data storage unit 209.

The manufacturability verification unit 347 of the CPU 300 verifiesmanufacturability in the exposure process of a correction target patternhaving a size W_(T) equal to or smaller than a threshold value T. Thecorrection unit 348 corrects the size W_(T) equal to or smaller than thethreshold value T of the correction target pattern to a size W_(U)larger than the threshold value T by executing, e.g., a mask dataprocessing (MDP) program. The correction unit 348 also generates thirddesign data by correcting the correction target pattern of first designdata. The optical proximity correction unit 349 executes opticalproximity correction (OPC) processing of the third design data byexecuting, e.g., an OPC program. The correction verification unit 350verifies whether a short circuit between patterns occurs in the thirddesign data which has undergone OPC processing and whether patternswhich should be connected are disconnected. The correction verificationunit 350 also verifies whether a violation of design rule occurs in thethird design data which has undergone OPC processing. Themanufacturability storage unit 208 of the data storage device 200 storesthe manufacturability verification result output from themanufacturability verification unit 347. The third design data storageunit 209 stores the third design data generated by the correction unit348. The remaining constituent elements of the pattern creation systemshown in FIG. 8 are the same as in the pattern creation system shown inFIG. 1, and a description thereof will be described.

A pattern creation method according to the second embodiment will bedescribed next with reference to the flowchart shown in FIG. 9.

(a) Steps S101 to S105 are executed in the same way as in the processingin FIG. 2. In the second embodiment, if the calculated characteristicdifference falls outside a tolerance R in step S106, the flow advancesto step S201. In step S201, the manufacturability verification unit 347verifies the manufacturability in exposure of a correction targetpattern having the size W_(T) equal to or smaller than the thresholdvalue T. For example, the manufacturability verification unit 347verifies the manufacturability of the correction target pattern bycalculating the optical intensity of a projected image corresponding tothe correction target pattern by exposure simulation using, e.g., aFourier transform program. After verification, the manufacturabilityverification unit 347 stores the manufacturability verification resultin the manufacturability storage unit 208.

(b) If it is determined by verification in step S201 that themanufacturability is more than a predetermined value because of, e.g.,the placement position and the distance to an adjacent pattern even whenthe correction target pattern has the size W_(T) equal to or smallerthan the threshold value T, the flow advances to step S301. In stepS301, a decision unit 346 decides to use the first design data tomanufacture the semiconductor integrated circuit. If it is determined instep S201 that the manufacturability of the correction target pattern isnot more than the predetermined value, the flow advances to step S202.In step S202, the correction unit 348 corrects the size W_(T) equal toor smaller than the threshold value T of the correction target patternto the size W_(U) larger than the threshold value T by executing, e.g.,an MDP program. The correction unit 348 decides the strength ofcorrection on the basis of the manufacturability verification resultstored in the manufacturability storage unit 208. After correction, thecorrection unit 348 stores, in the third design data storage unit 209,the third design data obtained by correcting the correction targetpattern of the first design data.

(c) In step S203, the optical proximity correction unit 349 reads outthe third design data from the third design data storage unit 209. Theoptical proximity correction unit 349 executes OPC processing of thethird design data by executing, e.g., an OPC program. Then, the opticalproximity correction unit 349 stores, in the third design data storageunit 209, the third design data which has undergone OPC processing. Instep S204, the correction verification unit 350 reads out the thirddesign data which has undergone OPC processing from the third designdata storage unit 209. The correction verification unit 350 verifieswhether a short circuit between patterns occurs in the third design datawhich has undergone OPC processing and whether patterns which should beconnected are disconnected. The correction verification unit 350 alsoverifies whether a violation of design rule occurs in the third designdata which has undergone OPC processing. If the correction verificationunit 350 determines that the third design data has undergone OPCprocessing appropriately, the decision unit 346 decides in step S205 touse the third design data to manufacture the semiconductor integratedcircuit, thus ending the pattern creation method according to the secondembodiment.

The third design data generated by the above-described pattern creationmethod according to the second embodiment is corrected to increase themanufacturability. For this reason, even when the semiconductorintegrated circuit is manufactured on the basis of the third designdata, the difficulty in the lithography process can be decreased. As aresult, the semiconductor integrated circuit can be manufactured at alow cost by using the third design data. It is verified in step S201that the first design data decided to use also have highmanufacturability. In this case, the semiconductor integrated circuitcan be manufactured at a low cost even by using the first design data.

Third Embodiment

An “overlapping area” provided in each cell in designing a semiconductorintegrated circuit on the basis of a cell library will be described. Inthe design process of a system LSI or ASIC device, a development methodof placing a plurality of standard cells and then routing them to eachother is widely employed. In this case, when a standard cell is placed,a pattern included in another standard cell to be placed adjacent to theplaced cell cannot be specified. For this reason, to prevent anyviolation of design rule regardless of the pattern of the standard cellto be placed adjacent, an “overlapping area 101” shown in FIG. 10 isarranged inside each of the standard cells. Placement of a functionalpattern to impart a function to the standard cell is inhibited in theoverlapping area 101. Functional patterns 103 a, 103 b, and 103 c areplaced in a pattern placement region 102 surrounded by the overlappingarea 101.

The minimum size (width) of the overlapping area must be ½ a minimumwidth b allowed for each layer in chip design, i.e., b/2. The exampleshown in FIG. 11 illustrates a cell pattern in which cells 61, 62, 63,and 64 are placed. In the cell 61, overlapping areas 161 a and 161 b areensured. In the cell 62, overlapping areas 162 a and 162 b are ensured.In the cell 63, overlapping areas 163 a and 163 b are ensured. In thecell 64, overlapping areas 164 a and 164 b are ensured. Each of theoverlapping areas 161 a, 161 b, 162 a, 162 b, 163 a, 163 b, 164 a, and164 b has the width b/2. Hence, functional patterns included in thecells 61, 62, 63, and 64 are always spaced apart by the minimum width ballowable by the design rule. However, some functional patterns need notalways be spaced apart by the minimum width b. For example, the minimumwidth b is unnecessary in a partial region 65 of the overlapping areas162 a and 164 a, the overlapping areas 162 a and 164 a need not beensured. In this case, ensuring an overlapping area in the partialregion 65 is redundant for design and impedes chip area reduction.

FIG. 12 is a flowchart showing a pattern data processing methodaccording to the third embodiment.

First, in step S300, the size of each of the overlapping areas of aplurality of cells included in the cell library is acquired. Next, instep S101, the cell place & router tool in the CPU places and routes thecells included in the cell library to form first design data. The firstdesign data is stored in a first design data storage unit 201.Subsequently, an extraction unit 341 reads out the first design data ofthe semiconductor integrated circuit from the first design data storageunit 201. Steps S102 to S113 are executed in the same way as in theprocessing in FIG. 2.

The pattern data processing method of the third embodiment can also beapplied to the method shown in FIG. 9. Referring to FIG. 9, after theabove-described operations in steps S300 and S101 are executed, stepsS102 to S301 are executed in the same way as in the processing in FIG.9.

In the pattern data processing method of the third embodiment, whetherpatterns ensured by combining overlapping areas in placing cells arenecessary for the device is stored in the database. Next, the cell place& router tool in the CPU places the cells included in the cell andcorrects or removes unnecessary patterns by referring to the database. Apattern may be replaced with another layer, or Boolean operation (AND)of layers may be executed. After that, if the correction or removal ofthe unnecessary patterns does not influence the performance of thesemiconductor integrated circuit to be manufactured, the semiconductorintegrated circuit is manufactured in accordance with the cell patternobtained by correcting or removing the unnecessary patterns.

In the third embodiment, the pattern data processing method is appliedto an implanted layer. However, the phenomenon that a pattern near theminimum design rule is formed by pattern contact in overlapping areaswithout influence on device performance also occurs in the well process,metal process, gate process, and diffusion process. Hence, the patterndata processing method of the third embodiment can also be applied tothe well process, metal process, gate process, and diffusion process.

Fourth Embodiment

In mask data processing (MDP), the manufacturability of the lithographyprocess is, increased by finely setting layout restrictions inaccordance with the increase in accuracy of RET ad OPC. To finely setthe layout restrictions, the design rule such as the restriction ofpattern placement positions must be made complex in consideration of theminimum line width of a pattern, the adjacent space width betweenpatterns, and an overlay error between layers.

In the lithography process; the minimum pattern size resoluble on awafer can be decreased theoretically by shortening the irradiation lightwavelength and increasing the NA of the projection optical system. Sincea short wavelength is difficult to realize, the mainstream of resolutionincrease means is increasing the NA. Especially, the resolution of a 1:1line & space (L/S) pattern can effectively be increased by. increasingthe NA. However, an increase in NA tends to decrease the lithographymargin of an isolated pattern. Hence, when a fine pattern is to beformed by a projection optical system with a high NA, the minimum sizeof an isolated pattern is restricted. More specifically, a design rulein which a size (line width) W of an isolated pattern (W1<W2<W3) and aninter-pattern distance S to an adjacent pattern (S1<S2<S3) satisfyfollowing relationships (1) to (3) needs to be created.

W1≦W<W2: S1≦S  (1)

W2≦W<W3: S2≦S  (2)

W3≦W: S3≦S  (3)

In the example shown in FIG. 13A, patterns 221 a and 221 b each havingthe line width W1 are placed at the inter-pattern distance S1. Theplacement of the patterns 221 a and 221 b satisfies the design rulebased on inequality (1). In the example shown in FIG. 13B, patterns 222a and 222 b each having the line width W3 are placed at theinter-pattern distance S1. The placement of the patterns 222 a and 222 bviolates the design rule based on inequality (3). In the example shownin FIG. 13C, patterns 223 a and 223 b each having the line width W1 areplaced at the inter-pattern. distance S3. The placement of the patterns223 a and 223 b satisfies the design rule based on inequality (1). Inthe example shown in FIG. 13D, patterns 224 a and 224 b each having theline width W3 are placed at the inter-pattern distance S3. The placementof the patterns 224 a and 224 b satisfies the design rule based oninequality (3). As shown in FIGS. 13A to 13D, in the lithographyprocess, providing a narrow space between wide patterns (lines)sometimes violates the design rule. Conventionally, to comply with thedesign rule defined by inequalities (1) to (3), “overlapping areas”having a width of ½ of S3 are uniformly ensured in cells each having apattern 225 with the line width W3, as shown in FIG. 14.

In a placement example 14A shown in FIG. 15, the widths of the“overlapping areas” of cells 241, 242, and 243 are uniformly set to ½ ofS3, and the cells 241, 242, and 243 are placed by the conventional dataprocessing method. This placement complies with the design rule becausethe inter-pattern distance S3 is ensured between a pattern 324 with theline width W3 in the cell 242 and a pattern 325 with the line width W3in the cell 243. However, the inter-pattern distance S3 ensured betweena pattern 424 with the line width W1 in the cell 241 and a pattern 425with the line width W1 in the cell 242 is redundant, resulting in anincrease in chip area after cell placement.

In a placement example 14B, the widths of the “overlapping areas” of thecells 241, 242, and 243 are uniformly set to ½ of S1. In this case, theinter-pattern distance S the pattern 424 with the line width W1 in thecell 241 and the pattern 425 with the line width W1 in the cell 242 isS1. However, this placement violates the design rule because theinter-pattern distance S between the pattern 324 with the line width W3in the cell 242 and the pattern 325 with the line width W3 in the cell243 is also S1. In this case, in the data processing method according tothe fourth embodiment, the inter-pattern distance S3 necessary betweenthe patterns 324 and 325 is read out by referring to the database inwhich the design tool stores inequalities (1) to (3). Hence, the cells242 and 243 are placed such that the inter-pattern distance S betweenthe patterns 324 and 325 becomes S3, as in a placement example 14C shownin FIG. 15.

A dummy cell may be placed between the cells 242 and 243. Instead ofchanging the placement positions of the cells 242 and 243, only thewidths of the “overlapping area” near the pattern 324 in the cell 242and the “overlapping area” near the pattern 325 in the cell 243 may bechanged to ½ of S3. If correction of the inter-pattern distance S has noinfluence on the performance of the semiconductor integrated circuit tobe manufactured, the semiconductor integrated circuit is manufactured onthe basis of layout data obtained by correcting the inter-patterndistance S.

According to the above-described pattern data processing method of thefourth embodiment, chip design can be done while minimizing the increasein chip area and satisfying the design rule. The data processing methodof the fourth embodiment may be incorporated in the cell placementprocess of cell place & route design or executed after the cellplacement process.

Fifth Embodiment

As described above, in a projection optical system with high NA, thelithography margin of an isolated pattern is small. In designing a chipby placing cells, terminating cells 141, 142, 143, and 144 placed atoutermost positions face a wide space, as shown in FIG. 16. For thisreason, the patterns of active regions such as diffusion regions near“overlapping areas” included in the terminating cells 141, 142, 143, and144 placed at outermost positions must have a large width to ensure thelithography margin.

However, whether a cell stored in a cell library should be placed at anend of a chip or at the center of a chip is unknown until actualplacement. Conventionally, for all cells included in a cell library, thepatterns of active regions near the “overlapping areas” are uniformlymade wide. However, when the patterns of active regions near the“overlapping areas” are uniformly wide, individual cell areas increase,resulting in an increase in the area of a chip designed by placing thecells.

To the contrary, according to a pattern data processing method of thefifth embodiment, after the design tool in the CPU places cells, onlythe widths of the active region of terminating cells are increased onthe basis of the area of the space that the terminating cells face. Atthis time, the design rule may refer to a relational expression betweenthe space area stored in a connected database and the minimum size of anactive region corresponding to the space area.

The lithography margin of an active region included in a terminatingcell may be ensured by placing a dummy cell on a side of the terminatingcell facing the space, i.e., between the terminating cell and the space,instead of correcting the size of the active region included in theterminating cell.

As described above, according to the embodiments of the presentinvention, a pattern creation method, pattern data processing method,pattern data processing program, and semiconductor integrated circuitmanufacturing method capable of decreasing the difficulty of thelithography process can be provided.

Other Embodiments

The present invention has been described above on the basis of theembodiments. The description and drawing as a part of the disclosureshould not be understood to limit the present invention. Those skilledin the art can see, from the disclosure, various alternate embodiments,examples, and application techniques. For example, the above-describedpattern creation method and data processing method can be expressed as aseries of processes or operations consecutive in a chronological order.Hence, the pattern creation method and data processing method shown inFIG. 2 and the like can be implemented by a computer program productwhich specifies a plurality of functions executed by a processor in theCPU 300 shown in FIG. 1 to cause it to execute the pattern creationmethod and data processing method. The computer program productindicates a recording medium or recording device inputtable/outputtableto/from the CPU 300. The recording medium includes a memory device,magnetic disk device, optical disk device, and any other device capableof recording a program. That is, the present invention should theunderstood to incorporate various embodiments that are not describedhere. Hence, the present invention is limited only by the specifyingitems of appropriate claims on the basis of the disclosure.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined. by the appended claims and their equivalents.

1-8. (canceled)
 9. A semiconductor device pattern data processing methodcomprising: acquiring a size of an overlapping area of each of aplurality of cells included in a cell library to be used to design asemiconductor device, the overlapping area being a region which isarranged inside the cell and in which placement of a functional patternto impart a function to the cell is inhibited; creating first designdata by placing the plurality of cells; calculating a firstcharacteristic of the semiconductor device on the basis of the firstdesign data; extracting a correction target region in which, of patternsformed by combining the overlapping areas upon placing the plurality ofcells, a pattern has a size not more than a threshold value; generatingsecond design data by correcting the correction target region containedin the first design data; calculating a second characteristic of thesemiconductor device on the basis of the second design data; checkingwhether a characteristic difference between the first characteristic andthe second characteristic falls within a tolerance; and creating patterndata of the semiconductor device on the basis of the second design datawhen the characteristic difference falls within the tolerance.
 10. Themethod according to claim 9, wherein the overlapping area is providednot to violate a design rule regardless of the pattern of the cell to beplaced adjacent.
 11. The method according to claim 9, wherein correctingthe correction target region includes erasing the correction targetregion from the first design data.
 12. The method according to claim 9,wherein correcting the correction target region includes correcting thesize of the correction target region, which is not more than thethreshold value, to a size more than the threshold value.
 13. The methodaccording to claim 9, wherein when the characteristic difference fallsoutside the tolerance, creating the pattern data on the basis of thefirst design data.
 14. The method according to claim 9, wherein thethreshold value includes a minimum size of an implantation target regionin an ion implantation process.
 15. The method according to claim 9,wherein letting T be the threshold value, 0.5≧T/(λ/NA) is satisfiedwhere λ is a wavelength of light in exposure, and NA is a numericalaperture of a projection optical system of an exposure apparatus used inexposure.
 16. The method according to claim 9, wherein each of the firstcharacteristic and the second characteristic includes at least one of atransistor characteristic, a circuit characteristic, an electricalcharacteristic, a timing characteristic, a wiring capacitancecharacteristic, and a wiring resistance characteristic.
 17. The methodaccording to claim 9, further comprising: verifying manufacturability inan exposure process of the correction target region having the size notmore than the threshold value when the characteristic difference fallsoutside the tolerance; creating pattern data of the semiconductor deviceon the basis of the first design data when the manufacturability is morethan a predetermined value; generating third design data by correctingthe correction target region contained in the first design data when themanufacturability is not more than the predetermined value; executingoptical proximity correction for the third design data; and creatingpattern data of the semiconductor device on the basis of the thirddesign data when optical proximity correction is appropriately done forthe third design data. 18-20. (canceled)